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preliminary specifications ?2003 silicon storage technology, inc. s71143-02-000 11/03 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. mpf is a trademark of silicon storage technology, inc. these specifications are subject to change without notice. 32 mbit (x16) multi-purpose flash sst39vf320 features: ? organized as 2m x16 single 2.7-3.6v read and write operations superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention low power consumption (typical values at 5 mhz) ? active current: 9 ma (typical) ? standby current: 3 a (typical) ? auto low power mode: 3 a (typical) sector-erase capability ? uniform 2 kword sectors block-erase capability ? uniform 32 kword blocks fast read access time ? 70 ns ? 90 ns latched address and data fast erase and word-program ? sector-erase time: 18 ms (typical) ? block-erase time: 18 ms (typical) ? chip-erase time: 40 ms (typical) ? word-program time: 7 s (typical) ? chip rewrite time: 15 seconds (typical) automatic write timing ? internal v pp generation end-of-write detection ? toggle bit ? data# polling cmos i/o compatibility jedec standard ? flash eeprom pinouts and command sets packages available ? 48-lead tsop (12mm x 20mm) ? 48-ball tfbga (6mm x 8mm) product description the sst39vf320 devices are 2m x16 cmos multi-pur- pose flash (mpf) manufactured with sst's proprietary, high performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst39vf320 write (program or erase) with a 2.7-3.6v power supply. featuring high performance word-program, the sst39vf320 devices provide a typical word-program time of 7 sec. the devices use toggle bit or data# polling to indicate the completion of program operation. to protect against inadvertent write, these devices have on-chip hard- ware and software data protection schemes. designed, manufactured, and tested for a wide spectrum of applica- tions, the sst39vf320 are offered with a guaranteed typi- cal endurance of 100,000 cycles. data retention is rated at greater than 100 years. the sst39vf320 devices are suited for applications that require convenient and economical updating of program, configuration, or data memory. for all system applications, the sst39vf320 significantly improve performance and reliability, while lowering power consumption. the sst39vf320 inherently use less energy during erase and program than alternative flash technologies. the total energy consumed is a function of the applied voltage, cur- rent, and time of application. since for any given voltage range, the superflash technology uses less current to pro- gram and has a shorter erase time, the total energy con- sumed during any erase or program operation is less than alternative flash technologies. the devices also improve flexibility while lowering the cost for program, data, and con- figuration storage applications. the superflash technology provides fixed erase and pro- gram times, independent of the number of erase/program cycles that have occurred. therefore the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose erase and program times increase with accumulated erase/pro- gram cycles. to meet high density, surface mount requirements, the sst39vf320 is offered in 48-lead tsop and 48-ball tfbga packages. see figures 1 and 2 for pinouts. device operation commands are used to initiate the memory operation func- tions of the device. commands are written to the device using standard microprocessor write sequences. a com- mand is written by asserting we# low while keeping ce# low. the address bus is latched on the falling edge of we# or ce#, whichever occurs last. the data bus is latched on the rising edge of we# or ce#, whichever occurs first. sst39vf3202.7v 32mb (x16) mpf memory
2 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 the sst39vf320 also have the auto low power mode which puts the device in a near standby mode after data has been accessed with a valid read operation. this reduces the i dd active read current from typically 9 ma to typically 3 a. the auto low power mode reduces the typi- cal i dd active read current to the range of 2 ma/mhz of read cycle time. the device exits the auto low power mode with any address transition or control signal transition used to initiate another read cycle, with no access time penalty. note that the device does not enter auto low power mode after power-up with ce# held steadily low until the first address transition or ce# is driven high. read the read operation of the sst39vf320 is controlled by ce# and oe#, both have to be low for the system to obtain data from the outputs. ce# is used for device selection. when ce# is high, the chip is deselected and only standby power is consumed. oe# is the output control and is used to gate data from the output pins. the data bus is in high impedance state when either ce# or oe# is high. refer to the read cycle timing diagram for further details (figure 3). word-program operation the sst39vf320 are programmed on a word-by-word basis. before programming, the sector where the word exists must be fully erased. the program operation is accomplished in three steps. the first step is the three-byte load sequence for software data protection. the second step is to load word address and word data. during the word-program operation, the addresses are latched on the falling edge of either ce# or we#, whichever occurs last. the data is latched on the rising edge of either ce# or we#, whichever occurs first. the third step is the internal program operation which is initiated after the rising edge of the fourth we# or ce#, whichever occurs first. the pro- gram operation, once initiated, will be completed within 10 s. see figures 4 and 5 for we# and ce# controlled pro- gram operation timing diagrams and figure 16 for flow- charts. during the program operation, the only valid reads are data# polling and toggle bit. during the internal pro- gram operation, the host is free to perform additional tasks. any commands issued during the internal program opera- tion are ignored. sector/block-erase operation the sector- (or block-) erase operation allows the system to erase the device on a sector-by-sector (or block-by- block) basis. the sst39vf320 offer both sector-erase and block-erase modes. the sector architecture is based on uniform sector size of 2 kword. the block-erase mode is based on uniform block size of 32 kword. the sector- erase operation is initiated by executing a six-byte com- mand sequence with sector-erase command (30h) and sector address (sa) in the last bus cycle. the block-erase operation is initiated by executing a six-byte command sequence with block-erase command (50h) and block address (ba) in the last bus cycle. the sector or block address is latched on the falling edge of the sixth we# pulse, while the command (30h or 50h) is latched on the rising edge of the sixth we# pulse. the internal erase operation begins after the sixth we# pulse. the end-of- erase operation can be determined using either data# polling or toggle bit methods. see figures 9 and 10 for tim- ing waveforms. any commands issued during the sector- or block-erase operation are ignored. chip-erase operation the sst39vf320 provide a chip-erase operation, which allows the user to erase the entire memory array to the ?1? state. this is useful when the entire device must be quickly erased. the chip-erase operation is initiated by executing a six- byte command sequence with chip-erase command (10h) at address 5555h in the last byte sequence. the erase operation begins with the rising edge of the sixth we# or ce#, whichever occurs first. during the erase operation, the only valid read is toggle bit or data# polling. see table 4 for the command sequence, figure 8 for timing diagram, and figure 19 for the flowchart. any commands issued dur- ing the chip-erase operation are ignored. write operation status detection the sst39vf320 provide two software means to detect the completion of a write (program or erase) cycle, in order to optimize the system write cycle time. the software detection includes two status bits: data# polling (dq 7 ) and to g g l e b i t ( d q 6 ). the end-of-write detection mode is enabled after the rising edge of we#, which initiates the internal program or erase operation. the actual completion of the nonvolatile write is asynchro- nous with the system; therefore, either a data# polling or toggle bit read may be simultaneous with the completion of the write cycle. if this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to con- flict with either dq 7 or dq 6 . in order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. if both reads are valid, then the device has completed the write cycle, otherwise the rejec- tion is valid.
preliminary specifications 32 mbit multi-purpose flash sst39vf320 3 ?2003 silicon storage technology, inc. s71143-02-000 11/03 data# polling (dq 7 ) when the sst39vf320 are in the internal program opera- tion, any attempt to read dq 7 will produce the complement of the true data. once the program operation is completed, dq 7 will produce true data. note that even though dq 7 may have valid data immediately following the completion of an internal write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive read cycles after an interval of 1 s. during internal erase operation, any attempt to read dq 7 will produce a ?0?. once the internal erase operation is completed, dq 7 will produce a ?1?. the data# polling is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sector-, block- or chip-erase, the data# polling is valid after the rising edge of sixth we# (or ce#) pulse. see figure 6 for data# polling timing diagram and figure 17 for a flowchart. toggle bit (dq 6 ) during the internal program or erase operation, any con- secutive attempts to read dq 6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. when the internal program or erase operation is completed, the dq 6 bit will stop toggling. the toggle bit is valid after the rising edge of fourth we# (or ce#) pulse for program operation. for sec- tor-, block- or chip-erase, the toggle bit is valid after the rising edge of sixth we# (or ce#) pulse. see figure 7 for toggle bit timing diagram and figure 17 for a flowchart. data protection the sst39vf320 provide both hardware and software fea- tures to protect nonvolatile data from inadvertent writes. hardware data protection noise/glitch protection : a we# or ce# pulse of less than 5 ns will not initiate a write cycle. v dd power up/down detection : the write operation is inhibited when v dd is less than 1.5v. write inhibit mode : forcing oe# low, ce# high, or we# high will inhibit the write operation. this prevents inadvert- ent writes during power-up or power-down. software data protection (sdp) the sst39vf320 provide the jedec approved soft- ware data protection scheme for all data alteration oper- ations, i.e., program and erase. any program operation requires the inclusion of the three-byte sequence. the three-byte load sequence is used to initiate the program operation, providing optimal protection from inadvertent write operations, e.g., during the system power-up or power-down. any erase operation requires the inclusion of six-byte sequence. this group of devices are shipped with the software data protection permanently enabled. see table 4 for the specific software command codes. during sdp command sequence, invalid commands will abort the device to read mode within t rc . the contents of dq 15 -dq 8 can be v il or v ih , but no other value, during any sdp command sequence. common flash memory interface (cfi) the sst39vf320 also contain the cfi information to describe the characteristics of the device. in order to enter the cfi query mode, the system must load the three-byte sequence, similar to the software id entry com- mand. the last byte cycle of this command loads 98h (cfi query command) to address 5555h. once the device enters the cfi query mode, the system can read cfi data at the addresses given in tables 5 through 7. the system must write the cfi exit command to return to read mode from the cfi query mode. product identification the product identification mode identifies the devices as the sst39vf320 and manufacturer as sst. this mode may be accessed by software operations. users may use the software product identification operation to identify the part (i.e., using the device id) when using multiple manufacturers in the same socket. for details, see table 4 for software operation, figure 11 for the software id entry and read timing diagram, and figure 18 for the software id entry command sequence flowchart. product identification mode exit/ cfi mode exit in order to return to the standard read mode, the software product identification mode must be exited. exit is accom- plished by issuing the software id exit command sequence, which returns the device to the read mode. this command may also be used to reset the device to the read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. please note that the software id exit/ table 1: p roduct i dentification address data manufacturer?s id 0000h 00bfh device id sst39vf320 0001h 2783h t1.1 1143
4 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 cfi exit command is ignored during an internal program or erase operation. see table 4 for software command codes, figure 13 for timing waveform, and figure 18 for a flowchart. figure 1: p in a ssignments for 48- lead tsop y-decoder i/o buffers and data latches 1143 b1.1 address buffer & latches x-decoder dq 15 - dq 0 memory address oe# ce# we# superflash memory control logic f unctional b lock d iagram a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# nc nc nc nc a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 nc v ss dq15 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v dd dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# v ss ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1143 48-tsop ek p01.10 standard pinout top view die up sst39vf320 sst39vf320 sst39vf320
preliminary specifications 32 mbit multi-purpose flash sst39vf320 5 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 2: p in a ssignments for 48- ball tfbga table 2: p in d escription symbol pin name functions a 20 -a 0 address inputs to provide memory addresses. during sector-erase a 20 -a 11 address lines will select the sector. during block-erase a 20 -a 15 address lines will select the block. dq 15 -dq 0 data input/output to output data during read cycles and receive input data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe# or ce# is high. ce# chip enable to activate the device when ce# is low. oe# output enable to gate the data output buffers. we# write enable to control the write operations. v dd power supply to provide power supply voltage: 2.7-3.6v for sst39vf320 v ss ground nc no connection unconnected pins. t2.2 1143 table 3: o peration m odes s election mode ce# oe# we# dq address read v il v il v ih d out a in program v il v ih v il d in a in erase v il v ih v il x 1 1. x can be v il or v ih , but no other value sector or block address, xxh for chip-erase standby v ih xxhigh z x write inhibit x v il xhigh z/ d out x xxv ih high z/ d out x product identification software mode v il v il v ih see table 4 t3.1 1143 a13 a9 we# nc a7 a3 a12 a8 nc nc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a19 a20 a5 a1 a16 dq7 dq5 dq2 dq0 a0 nc dq14 dq12 dq10 dq8 ce# dq15 dq13 v dd dq11 dq9 oe# v ss dq6 dq4 dq3 dq1 v ss 1143 48-tfbga b3k p02a.3 sst39vf320 top view (balls facing down) 6 5 4 3 2 1 a b c d e f g h
6 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 table 4: s oftware c ommand s equence command sequence 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 addr 1 data 2 word-program 5555h aah 2aaah 55h 5555h a0h wa 3 data sector-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h sa x 4 30h block-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h ba x 4 50h chip-erase 5555h aah 2aaah 55h 5555h 80h 5555h aah 2aaah 55h 5555h 10h software id entry 5,6 5555h aah 2aaah 55h 5555h 90h cfi query entry 5 5555h aah 2aaah 55h 5555h 98h software id exit 7 /cfi exit xxh f0h software id exit 7 /cfi exit 5555h aah 2aaah 55h 5555h f0h t4.4 1143 1. address format a 14 -a 0 (hex), addresses a ms -a 15 can be v il or v ih , but no other value, for the command sequence a ms = most significant address a ms = a 20 for sst39vf320 2. dq 15 - dq 8 can be v il or v ih , but no other value, for the command sequence 3. wa = program word address 4. sa x for sector-erase; uses a ms -a 11 address lines ba x , for block-erase; uses a ms -a 15 address lines 5. the device does not remain in software product id mode if powered down. 6. with a ms -a 1 =0; sst manufacturer?s id= 00bfh, is read with a 0 = 0, sst39vf320 device id = 2783h, is read with a 0 = 1. 7. both software id exit operations are equivalent table 5: cfi q uery i dentification s tring 1 for sst39vf320 1. refer to cfi publication 100 for more details. address data data 10h 0051h query unique ascii string ?qry? 11h 0052h 12h 0059h 13h 0001h primary oem command set 14h 0007h 15h 0000h address for primary extended table 16h 0000h 17h 0000h alternate oem command set (00h = none exists) 18h 0000h 19h 0000h address for alternate oem extended table (00h = none exits) 1ah 0000h t5.1 1143
preliminary specifications 32 mbit multi-purpose flash sst39vf320 7 ?2003 silicon storage technology, inc. s71143-02-000 11/03 table 6: s ystem i nterface i nformation for sst39vf320 address data data 1bh 0027h v dd min (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1ch 0036h v dd max (program/erase) dq 7 -dq 4 : volts, dq 3 -dq 0 : 100 millivolts 1dh 0000h v pp min (00h = no v pp pin) 1eh 0000h v pp max (00h = no v pp pin) 1fh 0003h typical time out for word-program 2 n s (2 3 = 8 s) 20h 0000h typical time out for min size buffer program 2 n s (00h = not supported) 21h 0004h typical time out for individual sector/block-erase 2 n ms (2 4 = 16 ms) 22h 0005h typical time out for chip-erase 2 n ms (2 5 = 32 ms) 23h 0001h maximum time out for word-program 2 n times typical (2 1 x 2 3 = 16 s) 24h 0000h maximum time out for buffer program 2 n times typical 25h 0001h maximum time out for individual sector/block-erase 2 n times typical (2 1 x 2 4 = 32 ms) 26h 0001h maximum time out for chip-erase 2 n times typical (2 1 x 2 5 = 64 ms) t6.3 1143 table 7: d evice g eometry i nformation for sst39vf320 address data data 27h 0016h device size = 2 n bytes (16h = 22; 2 22 = 4mbyte) 28h 0001h flash device interface description; 0001h = x16-only asynchronous interface 29h 0000h 2ah 0000h maximum number of bytes in multi-byte write = 2 n (00h = not supported) 2bh 0000h 2ch 0002h number of erase sector/block sizes supported by device 2dh 00ffh sector information (y + 1 = number of sectors; z x 256b = sector size) 2eh 0003h y = 1023 + 1 = 1024 sectors (03ffh = 1023) 2fh 0010h 30h 0000h z = 16 x 256 bytes = 4 kbyte/sector (0010h = 16) 31h 003fh block information (y + 1 = number of blocks; z x 256b = block size) 32h 0000h y = 63 + 1 = 64 blocks (0007h = 7) 33h 0000h 34h 0001h z = 256 x 256 bytes = 64 kbyte/block (0100h = 256) t7.2 1143
8 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 absolute maximum stress ratings (applied conditions greater than those listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. exposure to absolute maximum stress rating conditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to v dd + 0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0v to v dd + 1.0v voltage on a 9 and a 21 pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 12.6v package power dissipation capability (ta = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount lead soldering temperature (3 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240c output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. outputs shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 2.7-3.6v industrial -40c to +85c 2.7-3.6v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . c l = 30 pf see figures 14 and 15
preliminary specifications 32 mbit multi-purpose flash sst39vf320 9 ?2003 silicon storage technology, inc. s71143-02-000 11/03 table 8: dc o perating c haracteristics v dd = 2.7-3.6v 1 symbol parameter limits test conditions min max units i dd power supply current address input=v ilt /v iht , at f=5 mhz, v dd =v dd max read 2 18 ma ce#=v il , oe#=we#=v ih , all i/os open program and erase 35 ma ce#=we#=v il , oe#=v ih i sb standby v dd current 20 a ce#=v ihc , v dd =v dd max i alp auto low power current 20 a ce#=v ilc , v dd =v dd max, all inputs=v ss or v dd , we#=v ihc i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.8 v dd =v dd min v ih input high voltage 0.7v dd vv dd =v dd max v ihc input high voltage (cmos) v dd -0.3 v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t8.11 1143 1. typical conditions for the active current shown on the front page of the data sheet are average values at 25c (room temperature), and v dd = 3.0v. not 100% tested. 2. the i dd current listed is typically less than 2ma/mhz, with oe# at v ih. typical v dd is 3.0v. table 9: r ecommended s ystem p ower - up t imings symbol parameter minimum units t pu-read 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. power-up to read operation 100 s t pu-write 1 power-up to program/erase operation 100 s t9.0 1143 table 10: c apacitance (ta = 25c, f=1 mhz, other pins open) parameter description test condition maximum c i/o 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. i/o pin capacitance v i/o = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t10.0 1143 table 11: r eliability c haracteristics symbol parameter minimum specification units test method n end 1,2 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. 2. n end endurance rating is qualified as a 10,000 cycle minimum for the whole device. a sector- or block-level rating would result in a higher minimum specification. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t11.3 1143
10 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 ac characteristics table 12: r ead c ycle t iming p arameters v dd = 2.7-3.6v symbol parameter sst39vf320-70 sst39vf320-90 units minmaxminmax t rc read cycle time 70 90 ns t ce chip enable access time 70 90 ns t aa address access time 70 90 ns t oe output enable access time 35 45 ns t clz 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. ce# low to active output 0 0 ns t olz 1 oe# low to active output 0 0 ns t chz 1 ce# high to high-z output 20 30 ns t ohz 1 oe# high to high-z output 20 30 ns t oh 1 output hold from address change 0 0 ns t12.1 1143 table 13: p rogram /e rase c ycle t iming p arameters symbol parameter min max units t bp word-program time 10 s t as address setup time 0 ns t ah address hold time 30 ns t cs we# and ce# setup time 0 ns t ch we# and ce# hold time 0 ns t oes oe# high setup time 0 ns t oeh oe# high hold time 10 ns t cp ce# pulse width 40 ns t wp we# pulse width 40 ns t wph 1 1. this parameter is measured only for init ial qualification and after a design or proces s change that could affect this paramet er. we# pulse width high 30 ns t cph 1 ce# pulse width high 30 ns t ds data setup time 30 ns t dh 1 data hold time 0 ns t ida 1 software id access and exit time 150 ns t se sector-erase 25 ms t be block-erase 25 ms t sce chip-erase 50 ms t13.2 1143
preliminary specifications 32 mbit multi-purpose flash sst39vf320 11 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 3: r ead c ycle t iming d iagram figure 4: we# c ontrolled p rogram c ycle t iming d iagram 1143 f03.1 address a 20-0 dq 15-0 we# oe# ce# t ce t rc t aa t oe t olz v ih high-z t clz t oh t chz high-z data valid data valid t ohz 1143 f04.2 address a 20-0 dq 15-0 t dh t wph t ds t wp t ah t as t ch t cs ce# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# we# t bp note: x can be v il or v ih , but no other value
12 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 5: ce# c ontrolled p rogram c ycle t iming d iagram figure 6: d ata # p olling t iming d iagram 1143 f05.2 address a 20-0 dq 15-0 t dh t cph t ds t cp t ah t as t ch t cs we# sw0 sw1 sw2 5555 2aaa 5555 addr xxaa xx55 xxa0 data internal program operation starts word (addr/data) oe# ce# t bp note: x can be v il or v ih , but no other value 1143 f06.1 address a 20-0 dq 7 data data # data # data we# oe# ce# t oeh t oe t ce t oes
preliminary specifications 32 mbit multi-purpose flash sst39vf320 13 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 7: t oggle b it t iming d iagram figure 8: we# c ontrolled c hip -e rase t iming d iagram 1143 f07.1 address a 20-0 dq 6 we# oe# ce# t oe t oeh t ce t oes two read cycles with same outputs 1143 f08.2 address a 20-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx10 xx55 xxaa xx80 xxaa 5555 oe# ce# six-byte code for chip-erase t sce t wp note: this device also supports ce# controlled chip-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) x can be v il or v ih , but no other value
14 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 9: we# c ontrolled b lock -e rase t iming d iagram figure 10: we# c ontrolled s ector -e rase t iming d iagram 1143 f17.2 address a 20-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx50 xx55 xxaa xx80 xxaa ba x oe# ce# six-byte code for block-erase t be t wp note: this device also supports ce# controlled block-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) ba x = block address x can be v il or v ih , but no other value 1143 f18.2 address a 20-0 dq 15-0 we# sw0 sw1 sw2 sw3 sw4 sw5 5555 2aaa 2aaa 5555 5555 xx55 xx30 xx55 xxaa xx80 xxaa sa x oe# ce# six-byte code for sector-erase t se t wp note: this device also supports ce# controlled sector-erase operation. the we# and ce# signals are interchageable as long as minimum timings are met. (see table 13) sa x = sector address x can be v il or v ih , but no other value
preliminary specifications 32 mbit multi-purpose flash sst39vf320 15 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 11: s oftware id e ntry and r ead figure 12: cfi q uery e ntry and r ead 1143 f09.2 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 0000 0001 oe# ce# three-byte sequence for software id entry t wp t wph t aa 00bf device id xx55 xxaa xx90 device id = 2783h for sst39vf320 note: x can be v il or v ih , but no other value 1143 f20.1 address a 14-0 t ida dq 15-0 we# sw0 sw1 sw2 5555 2aaa 5555 oe# ce# three-byte sequence for cfi query entry t wp t wph t aa xx55 xxaa xx98 note: x can be v il or v ih , but no other value
16 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 13: s oftware id e xit /cfi e xit 1143 f10.1 address a 14-0 dq 15-0 t ida t wp t whp we# sw0 sw1 sw2 5555 2aaa 5555 three-byte sequence for software id exit and reset oe# ce# xxaa xx55 xxf0 note: x can be v il or v ih , but no other value
preliminary specifications 32 mbit multi-purpose flash sst39vf320 17 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 14: ac i nput /o utput r eference w aveforms figure 15: a t est l oad e xample 1143 f11.0 reference points output input v it v iht v ilt v ot ac test inputs are driven at v iht (0.9 v dd ) for a logic ?1? and v ilt (0.1 v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v it (0.5 v dd ) and v ot (0.5 v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v it - v input te s t v ot - v output te s t v iht - v input high test v ilt - v input low test 1143 f12.0 to tester to dut c l
18 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 16: w ord -p rogram a lgorithm 1143 f13.2 start load data: xxaah address: 5555h load data: xx55h address: 2aaah load data: xxa0h address: 5555h load word address/word data wait for end of program (t bp , data# polling bit, or toggle bit operation) program completed x can be v il or v ih , but no other value
preliminary specifications 32 mbit multi-purpose flash sst39vf320 19 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 17: w ait o ptions 1143 f14.0 wait t bp , t sce, t se or t be program/erase initiated internal timer toggle bit ye s ye s no no program/erase completed does dq 6 match? read same word data# polling program/erase completed program/erase completed read word is dq 7 = true data? read dq 7 program/erase initiated program/erase initiated
20 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 18: s oftware id/cfi c ommand f lowcharts 1143 f15.1 load data: xxaah address: 5555h software id entry command sequence load data: xx55h address: 2aaah load data: xx90h address: 5555h wait t ida read software id load data: xxaah address: 5555h cfi query entry command sequence load data: xx55h address: 2aaah load data: xx98h address: 5555h wait t ida read cfi data load data: xxaah address: 5555h software id exit/cfi exit command sequence load data: xx55h address: 2aaah load data: xxf0h address: 5555h load data: xxf0h address: xxh return to normal operation wait t ida wait t ida return to normal operation x can be v il or v ih , but no other value
preliminary specifications 32 mbit multi-purpose flash sst39vf320 21 ?2003 silicon storage technology, inc. s71143-02-000 11/03 figure 19: e rase c ommand s equence 1143 f16.1 load data: xxaah address: 5555h chip-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx10h address: 5555h load data: xxaah address: 5555h wait t sce chip erased to ffffh load data: xxaah address: 5555h sector-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx30h address: sa x load data: xxaah address: 5555h wait t se sector erased to ffffh load data: xxaah address: 5555h block-erase command sequence load data: xx55h address: 2aaah load data: xx80h address: 5555h load data: xx55h address: 2aaah load data: xx50h address: ba x load data: xxaah address: 5555h wait t be block erased to ffffh x can be v il or v ih , but no other value
22 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 product ordering information valid combinations for sst39vf320 sst39vf320-70-4c-ek sst39vf320-70-4c-b3k SST39VF320-70-4C-EKE sst39vf320-70-4c-b3ke sst39vf320-90-4c-ek sst39vf320-90-4c-b3k sst39vf320-90-4c-eke sst39vf320-90-4c-b3ke sst39vf320-70-4i-ek sst39vf320-70-4i-b3k sst39vf320-70-4i-eke sst39vf320-70-4i-b3ke sst39vf320-90-4i-ek sst39vf320-90-4i-b3k sst39vf320-90-4i-eke sst39vf320-90-4i-b3ke note: valid combinations are those products in mass production or will be in mass production. consult your sst sales representative to confirm availability of valid combinations and to determine availability of new combinations. environmental attribute e = non-pb package modifier k = 48 balls or leads package type b3 = tfbga (0.8mm pitch, 6mm x 8mm) e = tsop (type 1, die up, 12mm x 20mm) temperature range c = commercial = 0c to +70c i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles read access speed 70 = 70 ns 90 = 90 ns device density 320 = 32 mbit voltag e v = 2.7-3.6v product series 39 = multi-purpose flash sst 39 vf 320 - 70 - 4c - ek e xx x x xxx -xxx -x x -xx x x
preliminary specifications 32 mbit multi-purpose flash sst39vf320 23 ?2003 silicon storage technology, inc. s71143-02-000 11/03 packaging diagrams 48- lead t hin s mall o utline p ackage (tsop) 12 mm x 20 mm sst p ackage c ode : ek 1.05 0.95 0.70 0.50 18.50 18.30 20.20 19.80 0.70 0.50 12.20 11.80 0.27 0.17 0.15 0.05 48-tsop-ek-8 note: 1. complies with jedec publication 95 mo-142 dd dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 1.20 max. 1mm 0?- 5? detail pin # 1 identifier 0. 50 bsc
24 preliminary specifications 32 mbit multi-purpose flash sst39vf320 ?2003 silicon storage technology, inc. s71143-02-000 11/03 48- ball t hin - profile , f ine - pitch b all g rid a rray (tfbga) 6 mm x 8 mm sst p ackage c ode : b3k table 14: r evision h istory number description date 00 initial release jan 2003 01 clarified the test conditions for power supply current parameter in table 8 on page 9 mar 2003 02 2004 data book updated the b3k package diagram added non-pb mpns and removed footnote. (see page 22) nov 2003 a1 corner h g f e d c b a a b c d e f g h bottom view top view side view 6 5 4 3 2 1 6 5 4 3 2 1 seating plane 0.35 0.05 1.10 0.10 0.12 6.00 0.20 0.45 0.05 (48x) a1 corner 8.00 0.20 0.80 4.00 0.80 5.60 48-tfbga-b3k-6x8-450mic-4 note: 1. complies with jedec publication 95, mo-210, variant 'ab-1', although some dimensions may be more stringent. 2. all linear dimensions are in millimeters. 3. coplanarity: 0.12 mm 4. ball opening size is 0.38 mm ( 0.05 mm) 1mm silicon storage technology, inc. 1171 sonora court sunnyvale, ca 94086 telephone 408-735-9110 fax 408-735-9036 www.superflash.com or www.sst.com

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